Develop and design microarchitecture for core clocking, reset, and power management IPs for next generation processors. Collaborate with architecture, design verification, and physical design teams to ensure the successful integration of IPs into the an overall processor design using cutting edge fabrication technology. Create detailed specifications and documentation for

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build t

Design of complex building blocks of a PLL including architecture development and transistor level circuit design Run pre tapeout verification flows to confirm design meets performance, power, reliability and timing requirements. Work closely with mask design engineers to deliver the physical design as well as define production/bench level test plans with post silicon cha

Provide advisement and coordination for RPPG leadership team to drive decision making processes and execution of the strategic business objectives. Develop collaterals (presentations, pre reads, communications) for the CVP on internal and external activities through original contribution and/or collaboration with executives and senior leaders across RPPG. Represent the CV